Floorplan

Goal :: Placement of different functional blocks inside the core of the chip

Inputs ::

Synthesized netlist, LEF, Pin location’s and floorplan constraints.

Outputs ::

Design bonded with technology with specified area, macro placement and fixed pin placement.

Calculation of Core Die Size and Aspect Ratio:

Core Size =(Standard Cell Area / Standard Cell Utilization) + 

                    ( Macro Area + Hallo)

Die Size= Core Size+ IO to Core Clearance  Area of Pad (Including IO Pitch Area) + Area of Bond longest Pad

Chip Utilization =Area of  [ Standard Cell + Macro + ( Pad , PadFiller , CornerPad )] / Area of Chip

IO pin placement:

Pins are placed based on the connectivity of different blocks at top level.

Care should taken by block owner

• Whether all pins are placed or not.
• Whether the pins placed on grid or not.
• Checking for overlapping.
• Check for proper metal layer used at different sides of the block.

Macro Placement

Macro placement should be done based on

• IO connectivity
• Macro to Macro connectivity
• Macro to Logic connectivity
• Naming convention
• Min spacing should maintain between macro in order to establish one set of power strips.
• Orientation
• Most of the cases macro’s should be placed along the boundaries of  the core.

Adding Blockages and Clusters

Blockages ::

• Placement blockage

• Non buffer blockage.

• Std cell blockage.

• Routing blockage

• Halo

Clusters::

• Inclusive and Exclusive in Magma Tool