Clock net is one of the High Fanout Net(HFN)s.
The clock buffers are designed with some special property like high drive strength and less delay. Clock buffers have equal rise and fall
time. This prevents duty cycle of clock signal from changing when it passes through a chain of
clock buffers.
Normal buffers are designed with W/L ratio such that sum of rise time and fall time is minimum.They too are designed for higher drive strength.
Nice explaination,
ReplyDeleteIn simple, the rise and fall transition time for a normal buffer may varies from one clock cycle to other clock cycle.
where as in clock buffers the ris and fall transitions are uniform for every clock cycle.