Clock Gating

Clock Gating:

In order to reduce dynamic power consumption for a group of flipflops in design can be acheived by this technique. Some of the flops may not be active for a while of time, but remaining design in active.

Propagating a clock for the inactive part of design causes more power consumption ,to avoid this we are turning off the clock to the particular part of design is commonly known as clock gating. 

Two types of clock gating: 
 

Latch free clock gating:

An AND gate with two inputs,among them one input is enable signal and other is clock.The output of the  latch free clock gating may produce unwanted glitches due to sudden changes in enable signal .

In order to avoid these glitches , we are prefering latch based clock gating.

Latch based clock gating;

The following figures explains usage of negative level and positive level triggered latches.

                                                                    Fig:1

Fig 2:

  
If we use positive level triggered latch it will give some glitches (pulses). In the above figure (positive level latch), the ON period of output clock is reduced. So duty cycle of the clock also changes.

So for clock gating , it is preferable to use negative level latch as shown in the fig 1