Specifying Muxed clocks in crosstalk environment

Specifying MUXed Clocks in

Crosstalk Environment

# create parent clock

create_clock -period 10 CLK

creating a primary clock with period 10ns and name CLK

# create divide-by-2, divide-by-4 generated clocks

create_generated_clock -name CLKdiv2 -divide_by 2 FFdiv2/Q -source Ffdiv2/CK

generating a clock with name CLKdiv2 with primary clock as source and the output will be at Q pin of Ffdiv2.

The clock name on net2 (n2) will be CLKdiv2

create_generated_clock -name CLKdiv4 -divide_by 4 FFdiv4/Q -source Ffdiv4/CK

generating a clock with name CLKdiv4 with primary clock as source and the output will be at Q pin of Ffdiv4.

The clock name on net3 (n3) will be CLKdiv2

# create "MUXed" versions of all clocks arriving at MUX

normally we have only one output at mux,
If the case analysis is not specified Prime time considers all inputs to analyze.

create_generated_clock -name CLK_mux -combinational UMUX/A -source UMUX/A

the clock from clock source CLK will be changed at the input A of Mux (means primary clock CLK is changed as CLK_mux).

create_generated_clock -name CLKdiv2_mux -combinational UMUX/B -source UMUX/B

the clock from net n2 CLKdiv2 will be changed at the input B of the Mux (means CLKdiv2 is changed as CLKdiv2_mux).

create_generated_clock -name CLKdiv4_mux -combinational UMUX/C -source UMUX/C

the clock from net n3 CLKdiv2 will be changed at the input C of the Mux (means CLKdiv4 is changed as CLKdiv4_mux).

As we dont have any case analysis here we can assume 3 clocks at the MUX output. (Tool assumes like this and start analyzing)

# create divide-by-3 versions of all clocks arriving at Ffdiv3   

MUX output pin as the source pin to FFDiv3 circuit

the no of output clocks available at the FFDiv3 will be 3.

create_generated_clock \

  -name CLK_mux_div3 -divide_by 3 FFdiv3/Q -source FFdiv3/CK -master CLK_mux -add

CLK_mux will be changed as CLK_mux_div3, master clock is CLK_mux

create_generated_clock \

  -name CLKdiv2_mux_div3 -divide_by 3 FFdiv3/Q -source FFdiv3/CK -master CLKdiv2_mux -add

CLKdiv2_mux will be changed as CLKdiv2_mux_div3 master clock is CLKdiv2_mux

create_generated_clock \

  -name CLKdiv4_mux_div3 -divide_by 3 FFdiv3/Q -source FFdiv3/CK -master CLKdiv4_mux -add

CLKdiv4_mux will be changed as CLKdiv4_mux_div3 master clock is CLKdiv4_mux.

-add --- adding clocks to existing clock node

-master the -master_clock option must be used to specify which of these clocks to use as the source of the generated clock

  

# apply physical exclusivity to all clock families (generated clocks included)

# which are exclusive due to statically switched MUX

set_clock_groups -physically_exclusive \

  -group {CLK_mux     CLK_mux_div3} \

  -group {CLKdiv2_mux CLKdiv2_mux_div3} \

  -group {CLKdiv4_mux CLKdiv4_mux_div3}

1. Asynchronous clocks which were not related eachother.

2.      Exclusive clocks were maynot active in the design but the same time during physical existance of clock signal may effect eachother which causes cross talk.

3. set_clock_groups deviudes the one group of clocks from all clocks in the design

 The use of a single -group option

tells timing tool to cut this group of clocks from all other clocks in

the design, including clocks that are created in the future.

In the Above command

      group 1: CLK_mux     CLK_mux_div3

      group 2: CLKdiv2_mux CLKdiv2_mux_div3

      group 3: CLKdiv4_mux CLKdiv4_mux_div3

# Set clkA and clkB to be mutually exclusive clocks.

set_clock_groups -logically_exclusive -group {clkA} -group {clkB}

# The previous command is equivalent to the following two commands.

set_false_path -from [get_clocks clkA] -to [get_clocks clkB]

set_false_path -from [get_clocks clkB] -to [get_clocks clkA]