How cell delays varies with PVT conditions...:

How cell delay will be evaluted.

 
    cell delay is function of input transition and output load.But cell delay also varies with PVT conditions.

PVT conditions::

• Process Variation :: Variations in the process parameters can be impurity concentration densities, oxide thicknesses and diffusion depths.

As process increases delay increases.

• Voltage variation:: The delay of a cell is dependent on the saturation current. In this way, the power supply inflects the propagation delay of a cell. Throughout a chip, the power supply is not constant and hence the propagation delay varies in a chip. 

As voltage increases cell drives faster i.e. delay decreases.

• Temperature variation::As we know mobility of electrons depends on temperature ,which effects the delay.

As temperature increases mobility of charge carriers decreases, hence delay increases.

HFN ( High Fanout Net ) Synthesis

HFN:
High Fanout Net

As all of us knows fanout of the clock signal is high. Apart from that few of the signals are existed in design like reset ,clear and scan enable signals and etc..

The signal nets which have more fanout compared to specified fanout is also known as HFN

we all know that
                set_max_fanout <some number> during synthesis this means we tell to the synthesis tool that more than the max_fanout number treat it as High fanout net.


 Why do we do this ?

As we understanding HFN has lot of load obviously it has huge capacitance.

And if we tried to report the timing it reports very huge cap violations and huge delays in the timing path.

So to avoid this huge delays in timing path we are setting the same net as HFN.

another way to set an HFN to synthesis tool: set_ideal_net <net name>

 This way the synthesis tool knows the specified net as a high fanout net and does not buffer them .

Floorplan

Goal :: Placement of different functional blocks inside the core of the chip

Inputs ::

Synthesized netlist, LEF, Pin location’s and floorplan constraints.

Outputs ::

Design bonded with technology with specified area, macro placement and fixed pin placement.

Calculation of Core Die Size and Aspect Ratio:

Core Size =(Standard Cell Area / Standard Cell Utilization) + 

                    ( Macro Area + Hallo)

Die Size= Core Size+ IO to Core Clearance  Area of Pad (Including IO Pitch Area) + Area of Bond longest Pad

Chip Utilization =Area of  [ Standard Cell + Macro + ( Pad , PadFiller , CornerPad )] / Area of Chip

IO pin placement:

Pins are placed based on the connectivity of different blocks at top level.

Care should taken by block owner

• Whether all pins are placed or not.
• Whether the pins placed on grid or not.
• Checking for overlapping.
• Check for proper metal layer used at different sides of the block.

Macro Placement

Macro placement should be done based on

• IO connectivity
• Macro to Macro connectivity
• Macro to Logic connectivity
• Naming convention
• Min spacing should maintain between macro in order to establish one set of power strips.
• Orientation
• Most of the cases macro’s should be placed along the boundaries of  the core.

Adding Blockages and Clusters

Blockages ::

• Placement blockage

• Non buffer blockage.

• Std cell blockage.

• Routing blockage

• Halo

Clusters::

• Inclusive and Exclusive in Magma Tool

Clock Gating

Clock Gating:

In order to reduce dynamic power consumption for a group of flipflops in design can be acheived by this technique. Some of the flops may not be active for a while of time, but remaining design in active.

Propagating a clock for the inactive part of design causes more power consumption ,to avoid this we are turning off the clock to the particular part of design is commonly known as clock gating. 

Two types of clock gating: 
 

Latch free clock gating:

An AND gate with two inputs,among them one input is enable signal and other is clock.The output of the  latch free clock gating may produce unwanted glitches due to sudden changes in enable signal .

In order to avoid these glitches , we are prefering latch based clock gating.

Latch based clock gating;

The following figures explains usage of negative level and positive level triggered latches.

                                                                    Fig:1

Fig 2:

  
If we use positive level triggered latch it will give some glitches (pulses). In the above figure (positive level latch), the ON period of output clock is reduced. So duty cycle of the clock also changes.

So for clock gating , it is preferable to use negative level latch as shown in the fig 1

What is the differnce between clock buffer and normal buffer?

Clock net is one of the High Fanout Net(HFN)s. 
The clock buffers are designed with some special property like high drive strength and less delay. Clock buffers have equal rise and fall
time. This prevents duty cycle of clock signal from changing when it passes through a chain of
clock buffers.
Normal buffers are designed with W/L ratio such that sum of rise time and fall time is minimum.They too are designed for higher drive strength.